Printed circuit boards (hereinafter also referred to as PCBs), chip carriers, and the like (these products referred to generally herein as circuitized substrates) typically are constructed in laminate form in which several layers of dielectric material and conductive material (laminates) are bonded together using relatively high temperature and pressure lamination processes. The conductive layers, typically of thin copper or copper alloy, are usually used in the formed substrate for providing electrical connections to and among various devices located on the surface of the substrate, examples of such devices being integrated circuits (semiconductor chips) and discrete passive devices, such as capacitors, resistors, inductors, and the like. The discrete passive devices occupy a relatively high percentage of the surface area of the completed substrate, which is undesirable from a future design aspect because of the increased need and demand for miniaturization in today's substrates and products containing same art. In order to increase the available substrate surface area (also often referred to as “real estate”), there have been a variety of efforts to include multiple functions (e.g. resistors, capacitors and the like) on a single component for mounting on a board. When passive devices are in such a configuration, these are often referred to collectively and individually as integral passive devices or the like, meaning that the functions are integrated into the singular component. Because of such external positioning, these components still utilize, albeit less than if in singular form, board “real estate.”
In response to the above limitations, there have been efforts expended to embed discrete passive components within the internal portions of the substrate, such components then referred to as embedded passive components. A capacitor or resistor designed for disposition within (e.g., between selected layers) a substrate may thus be referred to as an embedded integral passive component, or, more simply, an embedded resistor or capacitor. Such a capacitor thus provides internal capacitance while a resistor provides internal resistance. The result of this internal positioning is that it is unnecessary to also position such devices externally on the PCB's outer surface(s), thus saving valuable PCB surface area.
Some of the documents listed below, U.S. Pat. No. 6,021,050 in particular, describe the internal use of resistors as passive elements for a PCB. As stated in Ser. No. 11/031,074 (now U.S. Pat. No. 7,025,607), there have also been past attempts to provide internal capacitance and other internal conductive structures, components or devices (one good example being internal semiconductor chips) within circuitized substrates (PCBs), some of these including the use of nano-powders. The following are some examples of various substrate structures, including those with embedded components as described above, including those using nano-powders and those using alternative measures. The citation of these documents is not an admission that any are prior art to the present invention.
In U.S. Patent Application Publication 2005/0051360 A1, entitled “Polymer Thick-Film Resistive Paste, A Polymer Thick-Film Resistor And A Method And An Apparatus For The Manufacture Thereof,” there are described formulations, apparatus and a method of applying high thixotropic index polymer thick-film resistive pastes for making polymer thick-film resistors with improved tolerances by providing a squeegee with a blade tilted at an angle of 10 to 85 to the surface of the printed circuit board. The tilted blade causes a fluid rotational motion within the bead of the polymer thick-film resistive paste as the squeegee blade moves relative to the printed circuit board. This rotational motion increases the shear strain rate experienced by the paste within the bead and results in a more effective filling of the resistor-shaped cavity without including air bubbles, experiencing elastic recovery of the paste and, without surface fractures of the paste.
In U.S. Patent Application Publication 2005/0000728 A1, entitled “Wiring Board Provided With A Resistor And Process For Manufacturing The Same,” there is described a wiring board provided with a resistor, The board comprises an insulating substrate having a surface, wiring patterns formed on the surface, the wiring patterns including first and second electrodes spaced from each other by a certain distance, a first resistor (horizontal type resistor) formed on the surface, the first resistor having respective ends connected with the first and second electrodes, respectively, the wiring patterns further including a third electrode, occupying a first plane area on the surface, a second resistor (vertical type resistor) formed on the third electrode, a fourth electrode formed on the second resistor, and the second resistor, the fourth electrode being located in a second plane area within the first plane area.
In U.S. Patent Application Publication 2004/0231758 A1, entitled “Silver-Coated Particles, Method And Apparatus Of Manufacture, Silver-Containing Devices Made Therefrom,” there is described the use of silver-containing powders and a method and apparatus for manufacturing the silver-containing particles of high quality, of a small size and narrow size distribution. An aerosol is generated from liquid feed and sent to a furnace, where liquid in droplets in the aerosol is vaporized to permit formation of the desired particles, which are then collected in a particle collector. The aerosol generation involves preparation of a high quality aerosol, with a narrow droplet size distribution, with close control over droplet size and with a high droplet loading suitable for commercial applications.
In U.S. Patent Application Publication 2003/0146418 A1, entitled “Resistive Film,” there is described a resistive film for use in a potentiometer. The film is in contact with a movable wiper. The film includes a cured polymer resin and a cured thermosetting resin. Conductive particles of carbon black and graphite are dispersed in the film. The conductive particles cause the resins to be electrically resistive. Carbon nano-particles are also dispersed in the film. The nano-particles increase the wear resistance of the resistive film and reduce electrical noise as the wiper moves across the film.
In U.S. Pat. No. 6,967,138, entitled “Process For Manufacturing A Substrate With Embedded Capacitor,” there is described a process for manufacturing a substrate with an embedded capacitor in which a first metal wiring layer including a lower electrode pad is-formed on a substrate base. A dielectric layer is formed on the substrate base by a build-up coating procedure. A hole is formed in the dielectric layer to expose the lower electrode pad, and a medium material is then filled into the hole. The medium material is ground to have a ground surface coplanar to the dielectric layer. A second metal wiring layer including an upper electrode pad is formed on the dielectric layer, the upper electrode pad covers the ground surface of the medium material and is parallel to the lower electrode pad so as to form an embedded capacitor.
In U.S. Pat. No. 6,746,508, entitled “Nanosized Intermetallic Powders,” there is described the use of nanoparticles of intermetallic alloys such as FeA1, Fe3A1, NiA1, TiA1 and FeCoV which exhibit a wide variety of interesting structural, magnetic, catalytic, resistive and electronic, and bar coding applications. The nanosized powders can be used to make structural parts having enhanced mechanical properties, magnetic parts having enhanced magnetic saturation, catalyst materials having enhanced catalytic activity, thick film circuit elements having enhanced resolution, and screen printed images such as magnetic bar codes having enhanced magnetic properties. In contrast to bulk FeA1 materials which are nonmagnetic at room temperature, the FeA1 nanoparticles exhibit magnetic properties at room temperature.
U.S. Pat. No. 6,740,701, entitled “Resistive Film”, there is described a resistive film for use in a potentiometer. The film is in contact with a movable wiper. The film includes a cured polymer resin and a cured thermosetting resin. Conductive particles of carbon black and graphite are dispersed in the film. The conductive particles cause the resins to be electrically resistive. Carbon nano-particles are also dispersed in the film. The nano-particles increase the wear resistance of the resistive film and reduce electrical noise as the wiper moves across the film. In the preparation of an exemplary composition, a polymer solution is made by mixing 10-20 wt. percent of a polymer and 0-10 wt. percent thermosetting resin in 60-80 wt. percent N-methyl pyrrolidone, based upon the total composition. The polymer is mixed with both the conductive and nano-particles to form a paste with a fine particle size. At this point, surfactants and rheological additives may be added if desired to modify the properties of the resistive composition. The particle size range and viscosity of the paste is monitored to get a resistive paste suitable for application in position sensors. The milling time and milling quantity on the ball mill determines the final particle distribution, size and resulting rheology.
In U.S. Pat. No. 6,704,207, entitled “Device and Method for Interstitial Components in a Printed Circuit Board”, issued Mar. 9, 2004, there is described a printed circuit board (PCB) which includes a first layer having first and second surfaces, with an above-board device (e.g., an ASIC chip) mounted thereon. The PCB includes a second layer having third and fourth surfaces. One of the surfaces can include a recessed portion for securely holding an interstitial component. A “via”, electrically connecting the PCB layers, is also coupled to a lead of the interstitial component. The described interstitial components include components such as diodes, transistors, resistors, capacitors, thermocouples, and the like. In what appears to be the preferred embodiment, the interstitial component is a resistor having a similar size to a “0402” resistor (manufactured by Rohm Co.), which has a thickness of about 0.014 inches.
In U.S. Pat. No. 6,616,794, entitled “Integral Capacitance For Printed Circuit Board Using Dielectric Nanopowders” and issued Sep. 9, 2003, there is described a method for producing integral capacitance components for inclusion within printed circuit boards in which hydro-thermally prepared nano-powders permit the fabrication of dielectric layers that offer increased dielectric constants and are readily penetrated by micro-vias. In the method described in this patent, a slurry or suspension of a hydro-thermally prepared nano-powder and solvent is prepared. A suitable bonding material, such as a polymer, is mixed with the nano-powder slurry, to generate a composite mixture which is formed into a dielectric layer. The dielectric layer may be placed upon a conductive layer prior to curing, or conductive layers may be applied upon a cured dielectric layer, either by lamination or metallization processes, such as vapor deposition or sputtering.
In U.S. Pat. No. 6,544,651, entitled “High Dielectric Constant Nano-Structure Polymer-Ceramic Composite” and issued Apr. 3, 2003, there is described a polymer-ceramic composite having high dielectric constants formed using polymers containing a metal acetylacetonate (acacs) curing catalyst. In particular, a certain percentage of Co (III) may increase the dielectric constant of a certain epoxy. The high dielectric polymers are combined with fillers, preferably ceramic fillers, to form two phase composites having high dielectric constants. Composites having about 30 to about 90% volume ceramic loading and a high dielectric base polymer, preferably epoxy, were apparently found to have dielectric constants greater than about 60. Composites having dielectric constants greater than about 74 to about 150 are also mentioned in this patent. Also mentioned are embedded capacitors with capacitance densities of at least 25 nF/cm.sup.2, preferably at least 35 nF/cm.sup.2, most preferably 50 nF/cm.sup.2.
In U.S. Pat. No. 6,524,352, entitled “Method Of Making A Parallel Capacitor Laminate” and issued Feb. 25, 2003, there is defined a parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an inter-connector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.
In U.S. Pat. No. 6,500,350, entitled “Formation of Thin Film Resistors” and issued Dec. 31, 2002, there is described a method for forming a patterned layer of resistive material in electrical contact with a layer of electrically conducting material. A three-layer structure is formed which comprises a metal conductive layer, an intermediate layer formed of material which is degradable by a chemical etchant, and a layer of resistive material of sufficient porosity such that the chemical etchant for the intermediate layer may seep through the resistive material and chemically degrade the intermediate layer so that the resistive material may be ablated from the conductive layer wherever the intermediate layer is chemically degraded. A patterned photo-resist layer is formed on the resistive material layer. The resistive material layer is exposed to the chemical etchant for the intermediate layer so that the etchant seeps through the porous resistive material layer and degrades the intermediate layer. Then, portions of the resistive material layer are ablated away wherever the intermediate layer has been degraded.
In U.S. Pat. No. 6,446,317, entitled “Hybrid Capacitor And Method Of Fabrication Therefore”, and issued Sep. 10, 2002, there is described a hybrid capacitor associated with an integrated circuit package that provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor which is embedded within the package and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.
In U.S. Pat. No. 6,396,387, entitled “Resistors For Electronic Packaging” and issued May 28, 2002, there are described thin layer resistors which are formed on an insulating substrate, which resistors may be embedded within a printed circuit board. Preferred resistive materials are homogeneous mixtures of metals, such as platinum, and dielectric materials, such as silica or alumina. Even minor amounts of dielectric material admixed with a metal significantly increase the resistance of the metal. Preferably, the resistive material is deposited on the insulating substrate by combustion chemical vapor deposition (CCVD). In the case of zero valence metals and dielectric material, the homogeneous mixture is achieved by co-deposition of the metal and dielectric material by CCVD. To form discrete patches of the resistive material, substantially any metal-based resistor material, including those based on the noble metals, can be etched away. Thus, a layer of resistive material may be covered with a patterned resist, e.g., an exposed and developed photo-resist, and exposed portions of the underlying layer of resistive material etched away. This patent also describes the formation of thin layer resistors including the insulating substrate, discrete patches of a layer of resistive material, and conductive material in electrical contact with spaced-apart locations on the patches of resistive material layer, such conductive material providing for electrical connection of the resistive material patches with electronic circuitry. Such structures of insulating material, resistive material, and conductive material may be formed by selective etching procedures.
In U.S. Pat. No. 6,395,996, entitled “Multi-layered Substrate With Built-In Capacitor Design” and issued May 28, 2002, there is described a multi-layered substrate having built-in capacitors which are used to decouple high frequency noise generated by voltage fluctuations between a power plane and a ground plane of a multi-layered substrate. At least one kind of dielectric material, which has filled-in through holes between the power plane and the ground plane and includes a high dielectric constant, is used to form the built-in capacitors.
In U.S. Pat. No. 6,370,012, entitled “Capacitor Laminate For Use In A Printed Circuit Board And As An Inter-connector” and issued Apr. 9, 2002, there is described a parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an inter-connector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.
In U.S. Pat. No. 6,242,282, entitled “Circuit Chip Package and Fabrication Method”, issued Jun. 5, 2001, there is described a method for packaging a chip which includes the steps of providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, a substrate via extending from the first side to one of the second side metallized portions, and a chip via extending from the first side to the second side non-metallized portion. The method also includes positioning a chip on the second side with a chip pad of the chip being aligned with the chip via, and patterning connection metallization on selected portions of the first side of the interconnect layer and in the via so as to extend to the second side metallized portion and to the chip pad. About the chip is molded a “substrate” or other dielectric material.
In U.S. Pat. No. 6,207,595, entitled “Laminate and Method of Manufacture Thereof”, issued Mar. 27, 2001, there is described a fabric-resin dielectric material for use in a laminate structure and method of its manufacture. The resulting structure is adaptable for use in a printed circuit board or chip carrier substrate. The resin may be an epoxy resin such as is currently used on a large scale worldwide for “FR-4” composites. A resin material based on bismaleimide-triazine (BT) is also acceptable, this patent further adding that more preferably, the resin is a phenolically hardenable resin material as is known in the art, with a glass transition temperature of about 145 degrees Celsius (C.).
In U.S. Pat. No. 6,150,456, entitled “High Dielectric Constant Flexible Polyimide Film And Process Of Preparations, issued Nov. 21, 2000, there is described a flexible, high dielectric constant polyimide film composed of either a single layer of an adhesive thermoplastic polyimide film or a multilayer polyimide film having adhesive thermoplastic polyimide film layers bonded to one or both sides of the film and having dispersed in at least one of the polyimide layers from 4 to 85 weight % of a ferroelectric ceramic filler, such as barium titanate or polyimide-coated barium titanate, and having a dielectric constant of from 4 to 60. The high dielectric constant polyimide film can be used in electronic circuitry and electronic components such as multilayer printed circuits, flexible circuits, semiconductor packaging and buried (internal) film capacitors
In U.S. Pat. No. 6,084,306, entitled “Bridging Method of Interconnects for Integrated Circuit Packages”, issued Jul. 4, 2000, there is described an integrated circuit package having first and second layers, a plurality of routing pads being integral with the first layer, a plurality of upper and lower conduits, respectively, disposed on the upper and lower surfaces of the first layer, one of the upper conduits electrically connected to one of the lower conduits, a plurality of pads disposed on the second layer, vias that electrically connect the pads to the lower conduits and a chip adhered to the second layer having bonding pads, at least one of which is electrically connected to one of the routing pads.
In U.S. Pat. No. 6,068,782, entitled “Individual Embedded Capacitors For Laminated Printed Circuit Boards” and issued May 30, 2000, there is described a method of fabricating individual, embedded capacitors in multilayer printed circuit boards. The method is allegedly compatible of being performed using standard printed circuit board fabrication techniques. The capacitor fabrication is based on a sequential build-up technology employing a first pattern-able insulator. After patterning of the insulator, pattern grooves are filled with a high dielectric constant material, typically a polymer/ceramic composite. Capacitance values are defined by the pattern size, thickness and dielectric constant of the composite. Capacitor electrodes and other electrical circuitry can be created either by etching laminated copper, by metal evaporation or by depositing conductive ink.
In U.S. Pat. No. 6,021,050, entitled “Printed Circuit Boards With Integrated Passive Components And Method Of Making Same,” there is described a multi-layered printed circuit board having a plurality of buried passive elements and a method for producing the circuit board wherein the passive elements can include resistors, capacitors and inductors. The method includes the steps of manufacturing individual layers of the multi-layer printed circuit board with electrical circuits thereon and subsequently screening polymer inks having resistive, dielectric or magnetic values to form the resistors, capacitors and inductors. Each layer of the circuit board is cured to dry the polymer ink and thereafter the individual layers are bonded together to form the multi-layer board.
In U.S. Pat. No. 5,831,833, entitled “Bare Chip Mounting Printed Circuit Board and a Method of Manufacturing Thereof by Photo-etching”, issued Nov. 3, 1998, there is described a method of manufacturing a “bare chip” multi-layer printed circuit board in which arbitrary numbers of wiring circuit conductor layers and insulating layers are alternately stacked on one or both surfaces of a printed circuit board as a substrate, and a recessed portion with an upper opening capable of mounting and resin-encapsulating a bare chip part is formed on the surface of the printed circuit board. In what appears to be the preferred embodiment, one of the insulating layers is made from a photosensitive resin, and the bare chip part mounting recessed portion is formed by photo-etching the insulating layer made from the photosensitive resin.
In U.S. Pat. No. 5,426,263, entitled “Electronic Assembly Having a Double-sided Leadless Component”, issued Jun. 20, 1995, there is described an electronic assembly which has a double-sided leadless component and two printed circuit boards. The component has a plurality of electrical terminations or pads on both opposing major surfaces. Each of the printed circuit boards has a printed circuit pattern that has a plurality of pads that correspond to the electrical terminations on both sides of the double-sided leadless component. The electrical terminals on one side of the component are attached to the pads on the first board and the electrical terminals on the other side of the leadless component are attached to the pads on the second board. The printed circuit boards are joined together to form a multilayered circuit board so that the double-sided leadless component is buried or recessed inside. The component is attached to the pads of the printed circuit board using solder.
In U.S. Pat. No. 5,280,192, entitled “Three-dimensional Memory Card Structure With Internal Direct Chip Attachment”, issued Jan. 18, 1994, there is described a card structure which includes an internal three dimensional array of implanted semiconductor chips. The card structure includes a power core and a plurality of chip cores. Each chip core is joined to the power core on opposite surfaces of the power care, and each chip core includes a compensator core having a two dimensional array of chip wells. Each chip well allows for a respective one of the semiconductor chips to be implanted therein. Further, a compliant dielectric material is disposed on the major surfaces of the compensator core except at the bottoms of the chip wells. The compliant dielectric material has a low dielectric constant and has a thermal coefficient of expansion compatible with those of the semiconductor chips and the compensator core, so that thermal expansion stability with the chips and the compensator core is maintained.
In U.S. Pat. No. 5,162,977, entitled “Printed Circuit Board Having An Integrated Decoupling Capacitive Element” and issued Nov. 10, 1992, there is described a PCB which includes a high capacitance power distribution core, the manufacture of which is compatible with standard printed circuit board assembly technology. The high capacitance core consists of a ground plane and a power plane separated by a planar element having a high dielectric constant. The high dielectric constant material is typically glass fiber impregnated with a bonding material, such as epoxy resin loaded with a ferroelectric ceramic substance having a high dielectric constant. The ferroelectric ceramic substance is typically a nano-powder combined with an epoxy bonding material. According to this patent, the resulting capacitance of the power distribution core is sufficient to totally eliminate the need for decoupling capacitors on a PCB. Use of pre-fired and ground ceramic nano-powders in the dielectric layer poses obstacles for the formation of thru-holes (conductive holes permitting electronic communication between conductive layers of a PCB), however. Pre-fired and ground ceramic nano-powder particles have a typical dimension in the range of 500-20,000 nanometers (nm). Furthermore, the particle distribution in this range is generally rather broad, meaning that there could be a 10,000 nm particle alongside a 500 nm particle. The distribution within the dielectric layer of particles of different size often presents major obstacles to thru-hole formation where the thru-holes are of extremely small diameter, also referred to in the industry as micro-vias due to the presence of the larger particles. Another problem associated with pre-fired ceramic nano-powders is the ability for the dielectric layer to withstand substantial voltage without breakdown occurring across the layer. Typically, capacitance layers within a PCB are expected to withstand at least 300 volts (V) in order to qualify as a reliable component for PCB construction. The presence of the comparatively larger ceramic particles in pre-fired ceramic nano-powders within a capacitance layer prevents extremely thin layers from being used because the boundaries of contiguous large particles provide a path for voltage breakdown. This is even further undesirable because, as indicated by the equation cited above, greater planar capacitance may also be achieved by reducing the thickness of the dielectric layer. The thickness is thus limited by the size of the particles therein.
In U.S. Pat. No. 5,099,309, entitled “Three-dimensional Memory Card Structure With Internal Direct Chip Attachment”, issued Mar. 24, 1992, there is described a memory card structure containing an embedded three dimensional array of semiconductor memory chips. The card structure includes at least one memory core and at least one power core which are joined together in an overlapping relationship. Each memory core comprises a copper-invar-copper (CIC) thermal conductor plane having a two dimensional array of chip well locations on each side of the plane. Polytetrafluoroethylene (PTFE) covers the major surfaces of the thermal conductor plane except at the bottoms of the chip wells. Memory chips are placed in the chip wells and are covered by insulating and wiring levels. Each power core comprises at least one CIC electrical conductor plane and PTFE covering the major surfaces of the electrical conductor plane. Provision is made for providing electrical connection pathways and cooling pathways along vertical as well as horizontal planes internal to the card structure.
In U.S. Pat. No. 5,079,069, entitled “Capacitor Laminate For Use In Capacitive Printed Circuit Boards And Methods Of Manufacture” and issued Jan. 7, 1992, there is described a capacitor laminate which allegedly serves to provide a bypass capacitive function for devices mounted on the PCB, the capacitor laminate being formed of conventional conductive and dielectric layers whereby each individual external device is allegedly provided with capacitance by a proportional portion of the capacitor laminate and by borrowed capacitance from other portions of the capacitor laminate, the capacitive function of the capacitor laminate being dependent upon random firing or operation of the devices. That is, the resulting PCB still requires the utilization of external devices thereon, and thus does not afford the PCB external surface area real estate savings mentioned above which are desired and demanded in today's technology.
In U.S. Pat. No. 5,016,085, entitled “Hermetic package for integrated circuit chips, issued May 14, 1991, there is described a hermetic package which has an interior recess for holding a semiconductor chip. The recess is square and set at 45 degrees with respect to the rectangular exterior of the package. The package uses ceramic layers which make up the package's conductive planes with the interior opening stepped to provide connection points. The lowest layer having a chip opening therein may be left out of the assembly to provide a shallower chip opening recess. This of course is not the same as an internally formed capacitance or semiconductor component of the nature described above, but it does mention internal ceramic layers for a specified purpose as part of an internal structure.
The teachings of the above patents, publications and cited co-pending applications are incorporated herein by reference.
Commercially available dielectric powders which have been used in internal conductive structures such as mentioned in some of the above patents are-known to be produced by a high-temperature, solid-state reaction of a mixture of the appropriate stoichiometric amounts of oxides or oxide precursors (e.g., carbonates, hydroxides or nitrates) of barium, calcium, titanium, and the like. In such calcination processes, the reactants are wet-milled to accomplish a desired final mixture. The resulting slurry is dried and fired at elevated temperatures, sometimes as high as 1,300 degrees Celsius (C), to attain the desired solid state reactions. Thereafter, the fired product is milled to produce a powder. Although the pre-fired and ground dielectric formulations produced by solid phase reactions are acceptable for many electrical applications, these suffer from several disadvantages. First, the milling step may serve as a source of contaminants, which can adversely affect electrical properties. Second, the milled product may consist of irregularly shaped fractured aggregates which are often too large in size and possess a wide particle size distribution, 500-20,000 nm. Consequently, films produced using these powders are limited to thicknesses greater than the size of the largest particle. Thirdly, powder suspensions or composites produced using pre-fired ground ceramic powders must be used immediately after dispersion, due to the high sedimentation rates associated with large particles. The stable crystalline phase of barium titanate for particles greater than 200 nm is tetragonal and, at elevated temperatures, a large increase in dielectric constant occurs due to a phase transition. It is thus clear that methods of making PCBs which rely on the advantageous features of using nano-powders as part of the PCB's internal components or the like, such as those described in selected ones of the above patents, possess various undesirable aspects which are detrimental to providing a PCB with optimal functioning capabilities when it comes to internal resistance, capacitance or other electrical properties.
The above is particularly true when the desired final product attempts to meet today's miniaturization demands, including the utilization of high density patterns of signal lines and thru-holes (definition below) therein. As is known, extremely close positioning of such thru-holes and signal lines may result in discontinuities occurring therein, which will adversely affect the successful operation of the product, especially at high frequencies (which are also demanded in many products today). Such discontinuities may also result from what is referred to as thru-hole “stub”, in which energy from the high speed signals passing through such thru-holes “bounces off” the end of the thru-hole (called the “stub”). These reflections and resonances may serve to contribute to signal degradation, particularly, as stated, when the signal lines and/or thru-holes are positioned in close proximity to one another. The successful elimination of such discontinuities is thus highly desired for many of today's circuitized substrates, especially those intended to pass high speed signals using high density patterns of thru-holes and/or signal lines.
The present invention is particularly directed to substantially eliminating many of such discontinuities by the provision of an internal resistor material as part of the internal circuit structure. By doing so, the invention is able to reduce capacitance and increase high frequency resistance at strategic locations within the circuit, thus improving system performance. It is believed that an invention possessing such features, as well as others discernible from the teachings herein, will constitute a significant advancement in the art.